Phase change memory is a memory device which typically uses a chalcogenide material for the memory elements. A memory element is the unit that actually stores information. In operation, the phase change memory stores information on the memory element by changing the phase of the memory element between amorphous and crystalline phases. The chalcogenide material may exhibit either a crystalline or an amorphous phase, exhibiting a low or high conductivity. Generally, the amorphous phase has a low conductivity (high impedance) and is associated with a reset state (logic zero) and the crystalline phase has a high conductivity (low impedance) and is associated with a set state (logic one). The memory element may be included in a memory cell that also includes a selector, i.e., a select device coupled to the memory element. The select devices are configured to facilitate combining a plurality of memory elements into an array.
Phase change memory elements may be arranged in a cross-point memory array including row address lines and column address lines arranged in a grid. The row address lines and column address lines, called word lines (WLs) and bit lines (BLs), respectively, cross in the formation of the grid and each memory cell is coupled between a WL and a BL where the WL and BL cross (i.e., cross-point). It should be noted that row and column are terms of convenience used to provide a qualitative description of the arrangement of WLs and BLs in cross-point memory.
A memory cell (e.g., a target memory cell) may be selected by applying bias voltages to the WL and BL that cross at the target memory cell, i.e., WL select voltage, VSELWL, and BL select voltage, VSELBL, respectively. A resulting target cell differential bias voltage (VT—SEL=VSELBL−VSELWL) across the memory element is configured to be greater than a threshold select voltage (Vt) for the memory element. It is desirable that VT—SEL be large enough to reliably select the target cell but not so large as to inadvertently select other cells, particularly non-target cells included in the selected WL or selected BL.
One technique configured to ensure that VT—SEL is large enough while avoiding selecting non-target cells is to apply a debias (“C-cell bias”) voltage to deselected WLs and/or deselected BLs. C-cell bias is configured to reduce or maintain a bias voltage across non-target cells below Vt when an increased VT—SEL is applied to the target cell. The increased VT—SEL is configured to increase the likelihood that the target cell will be selected. Continuously maintaining C-cell bias (i.e., whether or not a memory access has been initiated) increases leakage current in a cross-point array and increases idle current draw and idle power consumption.
Another technique that is configured to ensure that VT—SEL is large enough while avoiding selecting non-target cells, enables C-cell bias for every memory cell selection operation. This technique is configured to avoid increasing leakage current and/or idle current draw but incurs a relatively high energy cost due to charging and discharging associated with establishing and removing the C-cell bias for every memory cell operation. Relatively large bus structures may be necessary to accommodate rapid charging of C-cell bias and/or relatively long delay times may be experienced to allow time enough for all of the memory cells to achieve C-cell bias prior to selecting the target cell.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.